Latch-up is the condition where parasitic devices inherent in many CMOS structures cause the CMOS structure to enter an electrical state unrelated to its normal operation. This is often manifested as an abnormal high current conduction state. The condition may be transient, it may disappear when the triggering stimulus is removed or it may be permanent in the sense that the structure becomes frozen in that state as long as power continues to be applied. It may revert to the same frozen state when power is reapplied. Unless the current in the latch-up state is somehow limited, it can also be destructive. Thus, latch-up is a condition to be avoided in CMOS devices and ICs, and latch-up immunity is a highly desired property.
It is well known that latch-up is an increasing problem with CMOS technologies as device and circuit dimensions are scaled down. A CMOS integrated circuit (IC) chip designer often faces the problem of how to optimize the structure in order to avoid latch-up. As device dimensions are reduced, the problem becomes more difficult since most of the prior art arrangements for improving latch-up immunity call for substantial increased device and/or circuit area. Thus, a need continues to exist for improved CMOS structures and methods wherein latch-up immunity is improved with minimum area penalty and without adverse effect on the other CMOS IC properties.